ASIC DFT Engineer
DFT Engineer for ASIC/Chip level ATPG
- Fort Collins, Colorado, United States
- Full-time
- On-site
- $110K–$176K per year
- Posted Nov 11, 2026
INDUSTRYSoftware & InternetSaaS & Enterprise Software
Responsibilities
- Understand Broadcom and customer DFT feature requirements and DPPM goals to define appropriate DFT specifications for the ASIC
- Implement DFT architectures, including Scan, MBIST, TAP, LBIST, IO, SerDes, and IP DFT integration
- Perform ATPG and verification at the ASIC/chip level, as well as rapid bring-up of ATE test patterns
- Collaborate closely with STA and design integration engineers for timing and design closure
- Generate, verify, and debug test vectors prior to tapeout release
- Validate and debug test vectors on ATE during silicon bring-up
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts
- Interface with customers, physical design teams, and global test engineering/manufacturing teams
- Work closely with IP DFT engineers and cross-functional stakeholders
- Debug customer-returned parts (RMA) on ATE
- Proficiency in scripting and automation (such as Python, TCL, or C++), with an emphasis on applying AI-augmented development to streamline test flows
- Develop innovative DFT solutions for advanced process nodes (3nm and beyond)
- Automate DFT and test vector generation flows
Requirements
- Bachelors in Electrical/Electronic/Computer Engineering
- Masters Degree in Electrical/Electronic/Computer Engineering
- Experience in a ASIC
Nice to have: In-Field testing solutions, ATE silicon bring-up, debug, and high-speed IP/interface testing (SerDes, DDR, PCIe, Ethernet, CXL, Tessent SSN)
Skills
DFT architecture and implementation (Scan, BIST, IO/Analog DFT, IJTAG/IEEE 1687, IEEE 1149.1/1149.6)Proficiency with EDA tools (DFT Compiler, TestKompress, TetraMax, FastScan)Memory and logic BIST strategies, verification, and debug (SRAM, CAM, eDRAM, ROM)Verilog codingTestbench developmentATPG pattern generationSimulationTiming constraints/Test-STADigital/analog circuit designDevice physicsSilicon manufacturingSynthesisTransistor reliabilityRoot-cause debugStatistical process controlData analysisDFT CompilerTestKompressTetraMaxFastScanPythonTCLC++
Benefits
- Medical
- dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- company paid holidays
- paid sick leave
- vacation time
- discretionary annual bonus
- new hire equity grant
- annual equity awards
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