ASIC Implementation Engineer
Physical Design Engineer in ASIC Products Division focusing on next generation AI designs.
- San Jose, California, United States
- Full-time
- On-site
- $144K–$230K per year
- Posted Nov 11, 2026
INDUSTRYEngineeringElectrical Engineering
Responsibilities
- Execution of Physical Design, Physical Verification, and Timing Closure
- Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
- EM/IR Analysis
- Place and Route
- Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
- Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
- Flow and Methodology Development
- Collaborating with IC Design RTL Engineers
Requirements
- Bachelor’s degree in Electrical Engineering or Electronics Engineering
Skills
TCL/PERL ScriptingProficiency in related EDA ToolsFull physical design cycle experience: RTL to Tape-outTiming closureSTAEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planningLayoutFlow and Methodology DevelopmentCollaboration with RTL Engineers
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave
- Vacation time
- Paid Family Leave
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