DFT ATPG Engineer
Design‑for‑Test Engineer on the ATPG team at NVIDIA, focusing on DFT architecture, verification, and post‑silicon validation for semiconductor chips.
- Yokneam, Israel
- Posted Nov 9, 2026
INDUSTRYHardware & ElectronicsSemiconductors
Responsibilities
- Take part in state‑of‑the‑art Design for Test/ATPG flows and implementation
- Own ATPG projects from architecture to pattern generation, verification and post‑silicon bring‑up
- Invent and maintain automation flows to reduce test time to production
Requirements
- BSc. in Electrical Engineering
- BSc. in Computer Engineering
Skills
Strong programming skills in scripting languagesKnowledge of DFT including scan, BIST, on‑chip scan compression, fault models, ATPG, and fault simulationExperience with Mentor TestKompress ATPG tool and retargeting flowProgramming languages: TCL, PERL, Python & Unix shell scriptsExperience with ATE and Silicon bring‑upTCLPERLPythonUnix shell scriptsMentor TestKompress ATPG toolATE
Full description
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