Digital Design Implementation Engineer

San Jose, California, United States
Posted Nov 10, 2026

INDUSTRYHardware & ElectronicsSemiconductors

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Responsibilities

Perform ASIC design implementation in logic synthesis, static timing analysis, and place and route
Develop and maintain implementation flows and scripts, and drive timing, power, and area closure
Perform timing signoff, including constraint development and checking, and resolve timing violations
Work with RTL design, DFT, and physical design teams to resolve implementation issues
Support silicon bring-up and commercialization

Requirements

BS or BE minimum in Electrical/Computer Engineering or a related field

Nice to have: Experience implementing high-speed designs such as SerDes/high-speed PHY or high-frequency digital blocks, Experience with advanced process nodes, clock tree synthesis, and multi-corner/multi-mode timing closure, Familiarity with low-power design methodology (UPF) and signoff checks (physical verification, IR/EM)

Skills

ASIC design implementationlogic synthesisstatic timing analysisplace and routeEDA tools such as Synopsys Design Compiler/Fusion Compiler/PrimeTime or Cadence Genus/Innovus/Tempusdigital designtiming conceptsconstraintsscripting in Tcl, Python, Perl, or shellSynopsys Design CompilerSynopsys Fusion CompilerSynopsys PrimeTimeCadence GenusCadence InnovusCadence TempusTclPython Perlshell

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Full description

Job description: Overview & Impact Samsung SoC R&D Lab in San Jose is seeking a talented, highly motivated individual to join our team as a Digital Design Implementation Engineer. You will work as part of a team taking digital designs for wireless communication systems and high-speed PHY from RTL to signoff-quality silicon. Job Responsibilities Perform ASIC design implementation in one or more of: logic synthesis, static timing analysis (STA), and place and route (PnR). Develop and maintain implementation flows and scripts, and drive timing, power, and area (PPA) closure. Perform timing signoff, including constraint (SDC) development and checking, and resolve timing violations. Work with RTL design, DFT, and physical design teams to resolve implementation issues. Support silicon bring-up and commercialization. Required Skills BS or BE minimum in Electrical/Computer Engineering or a related field, with 2+ years of ASIC design implementation experience in at least one of STA, synthesis, or PnR Hands-on experience with industry-standard EDA tools (for example Synopsys Design Compiler/Fusion Compiler/PrimeTime, or Cadence Genus/Innovus/Tempus) Solid understanding of digital design, timing concepts, and constraints Proficiency in scripting (Tcl, Python, Perl, or shell) Teamwork, dedication, strong communications and interpersonal skills Excellent communication skills both written and verbal Preferred Skills Experience implementing high-speed designs, such as SerDes/high-speed PHY or high-frequency digital blocks Experience with advanced process nodes, clock tree synthesis, and multi-corner/multi-mode (MCMM) timing closure Familiarity with low-power design methodology (UPF) and signoff checks (physical verification, IR/EM)