R&D Engineer IC Design
The role involves working on various phases of SoC DFT related activities including DFT architecture, test insertion, verification, pattern generation, coverage improvement, post silicon debug, and yield improvement.
- Bangalore, Karnataka, India
- Full-time
- On-site
- Posted Nov 2, 2026
INDUSTRYEngineeringSemiconductors
Responsibilities
- Work on SoC DFT architecture
- Test insertion and verification
- Pattern generation
- Coverage improvement
- Post silicon debug and yield improvement
- Work with Physical Design & STA team for DFT mode timing closure
- Direct interaction with external customers
- Supervise the work of other team members as required
Requirements
- Bachelor’s degree
- Master’s degree
- Experience in a ASIC
- Experience in a Semiconductors
Nice to have: perl, shell, Seimens-Mentor Graphics DFT tools, TestKompress, Fastscan
Skills
DFT conceptsATPGMBISTJTAGDFT insertion & verificationpattern generationcoverage improvementvector simulationpost-silicon debugscripting languagesperlshellTestKompressFastscan
Full description
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