- Markham, Ontario, Canada +1 more
IP Validation Design Engineer responsible for planning, validating, and debugging hardware IP for AMD SOC programs.
Locations (2)
- Markham, Ontario, Canada
- Vancouver, British Columbia, Canada
Responsibilities
- Drive planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs
- Define, document, execute and report overall functional test plan and validation strategy for a set of AMD IPs
- Drive technical innovation to enhance AMD's capabilities in IP validation
- Debug IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs
- Engage in pre-silicon ‘shift left’ activities with cross-functional teams
Requirements
- Bachelor’s or master’s degree majoring in EE, CS or related field