- Santa Clara, California, United States
- On-site
- Full-time · Principal
Lead the development of next-generation AI-native methodologies for silicon architecture, RTL generation, verification automation, and design optimization, driving innovation across AMD networking and infrastructure programs.
Responsibilities
- Define and lead AI-assisted methodologies for generating synthesizable RTL from high-level architectural specifications and programmable packet-processing pipelines.
- Develop automated techniques to optimize pipeline organization, lookup structures, memories, and datapaths for power, performance, area, and cost.
- Drive AI-assisted hardware architecture exploration, implementation, and design optimization.
- Lead automated verification generation, including reference models, testbenches, assertions, coverage plans, and regression environments.
- Establish methodologies to prove functional equivalence between programmable and generated implementations using simulation, formal verification, and differential testing.
Requirements
- PhD or equivalent industry experience in Computer Engineering, Electrical Engineering, Computer Science, or a related field
- Nice to have: AI-assisted engineering methodologies