As a Metrology Engineer you will be collaborating with process and integration guides to qualify Low and High NA EUV lithography processes and other technology development projects that directly shape future memory technologies. You will work hands-on with equipment, materials, layouts, and data, while collaborating with global partners to move innovations from R&D into high-volume manufacturing. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making.
Locations (3)
Albany, New York, United States
Boise, United States
Hiroshima
Compensation
$104,000.00 - $224,000.00 a year
Responsibilities
Develop and integrate metrology processes for advanced memory technologies
Perform material evaluations, reticle and layout development, OPC, overlay optimization, and process window analysis
Drive yield improvement, failure analysis, and device performance optimization
Partner with equipment vendors to evaluate tools and improve process capability
Document processes, communicate results, and support technology transfer to manufacturing
Requirements
M.S. or Ph.D. in Electrical or Electronics Engineering, Materials Science, Physics, Chemistry, Chemical Engineering, Computer Engineering, or other Engineering or Technical Degree relevant to Metrology
B.S. with 2+ years semiconductor processing experience with emphasis on metrology
As a Metrology Engineer you will be collaborating with process and integration guides to qualify Low and High NA EUV lithography processes and other technology development projects that directly shape future memory technologies.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $104,000.00 - $224,000.00 a year. Additional compensation may include benefits, bonuses and equity.
Responsibilities
Develop and integrate metrology processes for advanced memory technologies
Perform material evaluations, reticle and layout development, OPC, overlay optimization, and process window analysis
Drive yield improvement, failure analysis, and device performance optimization
Partner with equipment vendors to evaluate tools and improve process capability
Document processes, communicate results, and support technology transfer to manufacturing
Requirements
M.S. or Ph.D. in Electrical or Electronics Engineering, Materials Science, Physics, Chemistry, Chemical Engineering, Computer Engineering, or other Engineering or Technical Degree relevant to Metrology
B.S. with 2+ years semiconductor processing experience with emphasis on metrology
Lead technical development of lithography processes for quantum technologies, bridging advanced technology development and semiconductor manufacturing.
Compensation
$118,000.00 - $210,000.00
Responsibilities
Serve as the QTS technical authority for advanced optical and related lithography processes
Develop and optimize lithography processes supporting quantum device and module development
Lead evaluation of resist systems, coat/develop processes, exposure strategies, alignment approaches, and patterning schemes
Drive improvements in critical dimension control, overlay, pattern fidelity, defectivity, and process window
Develop patterning strategies for unconventional quantum structures, materials, substrates, and integration requirements
The Lithography Advanced Manufacturing Engineering (AME) SMTS will serve as a senior technical leader responsible for developing and enabling lithography capabilities supporting next-generation quantum technologies.
Locations (2)
New York, New York, United States
Malta
Compensation
$118,000.00 - $210,000.00
Responsibilities
Serve as the QTS technical authority for advanced optical and related lithography processes
Develop and optimize lithography processes supporting quantum device and module development
Lead evaluation of resist systems, coat/develop processes, exposure strategies, alignment approaches, and patterning schemes
Drive improvements in critical dimension control, overlay, pattern fidelity, defectivity, and process window
Develop patterning strategies for unconventional quantum structures, materials, substrates, and integration requirements