- Boise, Idaho, United States
Design and verify physical layouts of analog circuits for memory products, including floor planning, routing, and power bus designs, while collaborating with engineering teams across India, Japan, and the US.
Responsibilities
- Create physical layout of transistors, resistors, and capacitors for analog circuits used in memory products
- Build layouts that meet process rules and verify alignment with schematics
- Work on floor planning, routing, and power bus designs
- Support team in establishing IP Layout work modes, including layout standardization and workflow alignment
- Deliver quality layout on time, monitor layout quality, pass SPF, confirm with circuit designers, and deliver layout and DBR on time
Requirements
- Master’s degree in Electrical Engineering
- Master’s degree in Computer Engineering
- Master’s degree in related field