- Remote, United States
- Remote
- Full-time · Principal
- $190K–$280K per year
- 10+ years
Lead the implementation of complex SoCs for next-generation satellite and space systems, owning the full physical design flow from RTL handoff to GDSII.
Compensation
Base salary range for this role is $190,000 – $280,000 + equity in the company
Responsibilities
- Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
- Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
- Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
- Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
- Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- Nice to have: Radiation-hardened ASICs
- Nice to have: Chip-package co-design
- Nice to have: Advanced packaging (2.5D/3D)
- Nice to have: TSMC tapeouts