As a Senior FPGA Design & Timing Modeling Engineer, you will work at the intersection of FPGA circuit design, silicon characterization, and software device modeling. You will help translate the behavior and performance of AMD FPGA hardware into accurate timing models used by Vivado to compile, analyze, and optimize customer designs.
- Generate simulation based delays using existing hardware designs to match FPGA timing arcs as per the device model
- Develop automation flows to improve FPGA timing quality
- Drive silicon based characterization of FPGA resources and root cause any mis-correlation with the expected timing model
- Performance analysis on complex designs using Vivado tool
- Coordinate release readiness reviews and manage risk mitigation plans
- Bachelors or Masters degree in Computer Science/Electrical Engineering
- Nice to have: FPGA design implementation
- Nice to have: PrimeTime
- Nice to have: SPICE
- Nice to have: Vivado
FPGA Design and Timing Modeling EngineerNewAdvanced Micro Devices, Inc · San Jose, US
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