RAS Architect
RosaicLabs · Posted Oct 21, 2026
- Santa Clara, California, United States
- On-site
- Full-time · Senior
- 12+ years
- Visa sponsorship
Define resilience across multi-die computing systems, translating reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, and telemetry.
Responsibilities
- Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping
- Define fault detection, correction, logging, and diagnosis across compute engines and cores, caches, HBM and LPDDR memory, die-to-die and scale-up links, PCIe/CXL, and management agents
- Specify ECC, parity, residue checks, memory scrubbing, retirement or repair, and in-field screening to prevent and detect silent data corruption
- Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors
- Specify isolation, fencing, and degraded-operation behavior for compute units, cores or clusters, memory resources, links, and package-level failures
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
- Nice to have: Processor error-reporting architectures
- Nice to have: Firmware-first error handling
- Nice to have: BMC integration
- Nice to have: Fleet reliability telemetry