- Singapore, Singapore
- On-site
- Internship · Intern
- 0+ years
Internship in Wafer Edge Region Process Development focusing on eliminating wafer‑edge coating in the Pillar module.
Responsibilities
- Expand dataset and analytical framework
- Design experiments and analyze data
- Characterize wafer‑edge defects
- Develop safe approach for increasing run rate of coating‑free wafers
- Establish inline monitoring criteria
Requirements
- Master’s degree in Materials Science and Engineering, Chemical Engineering, Physics, Electrical and Electronic Engineering, or related discipline
- Nice to have: Familiarity with planar or 3D NAND memory process flows
- Nice to have: Industrial data‑analysis or yield‑analysis systems