- San Jose, California, United States
- Full-time · Senior
- $149K–$282K per year
- 2+ years
As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips.
Compensation
The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
- Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm)
- Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies
- Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools
- Implement and manage timing ECO strategies using tools like Prime Closure/PrimeTime
- Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements
Requirements
- Bachelors degree in Electrical Engineering
- Masters degree in Electrical Engineering
- PhD in Electrical Engineering
- Nice to have: TCL scripting
- Nice to have: Python scripting