This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end to end memory system architectures, to guide long term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $143,000.00 - $398,000.00 a year
Responsibilities
Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance.
Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach
Drive long‑term memory technology packaging strategy and influence industry standards
Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge-AI and datacenter memory products
Serve as a technical interface to internal partners, customers, BUs, senior leaders.
Requirements
Master’s degree or equivalent practical experience in EE, CE, CS, or related field
This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end to end memory system architectures, to guide long term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $143,000.00 - $398,000.00 a year
Responsibilities
Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance.
Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach
Drive long‑term memory technology packaging strategy and influence industry standards
Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge-AI and datacenter memory products
Serve as a technical interface to internal partners, customers, BUs, senior leaders.
Requirements
Master’s degree or equivalent practical experience in EE, CE, CS, or related field
This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end to end memory system architectures, to guide long term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron.
Compensation
The US base salary range that Micron Technology estimates it could pay for this full-time position is: $143,000.00 - $398,000.00 a year
Responsibilities
Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance
Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach
Drive long‑term memory technology packaging strategy and influence industry standards
Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge-AI and datacenter memory products
Serve as a technical interface to internal partners, customers, BUs, senior leaders
Requirements
Master’s degree or equivalent practical experience in EE, CE, CS, or related field
Lead technical pathfinding and architecture for next‑generation memory packaging solutions across silicon, package, board, and system layers.
Compensation
$143,000.00 - $398,000.00 a year
Responsibilities
Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance.
Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach.
Drive long‑term memory technology packaging strategy and influence industry standards.
Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge‑AI and datacenter memory products.
Serve as a technical interface to internal partners, customers, BUs, senior leaders.
Requirements
Master’s degree or equivalent practical experience in EE, CE, CS, or related field
Master’s degree or PhD in a related technical field
Nice to have: recognized technical leadership across multiple products
Nice to have: experience in signal and power integrity analysis
Nice to have: experience in mechanical and reliability analysis
Memory Package Integration ArchitectNewMicron Technology · Boise, US