- San Jose, California, United States
- Hybrid
- Full-time · Mid
- $126K–$177K per year
- 2+ years
Seeking a qualified Signal and Power Integrity Engineer to help develop next-generation ASIC packaging to help define, design and verify ASIC packaging to be deployed in a range of Cisco platforms.
Compensation
The starting salary range posted for this position is $125,700.00 to $176,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
- Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products.
- Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB.
- Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting.
- Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules.
- Perform SI/PI characterization, validation, and debug of high-speed systems and packages.
Requirements
- Bachelors
- Masters
- Nice to have: High-bandwidth memory (HBM)
- Nice to have: High-speed memory interface SI
- Nice to have: Die-to-die interfaces (UCIe)