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1–2 jobs· newest first

ASIC III – AMZ010066
Amazon · Austin, US
$203K–$215KOn-site · Full-time
Mixed Signal SVE Engineer
Qualcomm · San Diego, US
$146K–$218K

+10K new in the last hour

ASIC III – AMZ010066

Amazon · Posted Nov 6, 2026

Austin, Texas, United States
On-site
Full-time
$203K–$215K per year
7+ years

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Compensation

Salary Range $202,779 - $215,300 / year.

Responsibilities

Design and validate high-bandwidth memory and DDR memory physical layer interfaces for machine learning accelerator chips and system-on-chip architectures
Integrate third-party intellectual property blocks into complex system-on-chip designs and perform advanced 2.5D packaging design for memory subsystems
Perform post-silicon validation and characterization of memory subsystems including bring-up, debug, and performance optimization
Define and implement boot-up initialization sequences, reset flows, and training algorithms for memory controllers and physical layer circuits
Collaborate with physical design teams to define timing constraints and review clock distribution networks for memory interfaces

Requirements

Master’s degree in Electrical Engineering or Computer Engineering
Bachelor’s degree in Electrical Engineering or Computer Engineering

Skills

silicon development system-on-chip design input/output subsystems memory interface design DDR and HBM memory protocols JEDEC specifications training algorithms timing parameters controller configuration intellectual property integration advanced silicon design methodologies cross-functional team leadership post-silicon bring-up validation working with third-party IP vendors memory device manufacturers

Benefits

Medical benefits
Financial benefits
Other benefits

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Mixed Signal SVE Engineer

Qualcomm · Posted Nov 5, 2026

San Diego, California, United States
$146K–$218K per year
4+ years

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Lead bring‑up, debugging, and optimization of DDR/SerDes PHYs across post‑silicon teams and provide post‑release support for PHY‑related customer issues.

Compensation

$145,600.00 - $218,400.00

Responsibilities

Lead bring‑up, debugging, and optimization of DDR/SerDes PHYs across post‑silicon teams.
Proactively identify and resolve issues to ensure successful product launches.
Provide post‑release support for PHY‑related customer issues.
Develop firmware and execute regression testing.
Generate clear and detailed test reports and documentation.

Requirements

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field

Skills

DDR/SerDes test development debugging characterization firmware development Python scripting

JEDEC specifications

PHY circuitry fundamentals

signal integrity

lab instruments

machine learning

statistical modeling

data visualization

automated pipelines

spectrum analyzers

logic analyzers

Benefits

competitive annual discretionary bonus program
annual RSU grants
highly competitive benefits package

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