FY27 Intern - Design For Test for a Secure Asynchronous IP - 6 months, Montbonnot
Qualcomm · Posted Nov 9, 2026
- Montbonnot-Saint-Martin, Auvergne-Rhône-Alpes, France
- Internship · Intern
Internship focused on improving test capabilities for the TESIC Secure Enclave IP.
Responsibilities
- Improve test capabilities of the TESIC IP, including MBIST, Design for Test, test coverage and fault analysis
- Adapt well-known tools to the security context and asynchronous logic features
Requirements
- Ongoing Master in Integrated Electronic Systems
- Internship for Master 2
- Nice to have: Knowledge of security for Embedded Systems