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1–2 jobs· newest first

Sr. Staff Performance Tuning Engineer - CPU PMU & VirtualizationNew
NIO USA, INC · San Jose, US
$192K–$250KFull-time · Senior
AI System Architect (NPU / GPU / Interconnect)
Qualcomm · Shanghai, China

+10K new in the last hour

N

Sr. Staff Performance Tuning Engineer - CPU PMU & Virtualization

NIO USA, INC · Posted Jun 18, 2026

San Jose, California, United States
Full-time · Senior
$192K–$250K per year
8+ years

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Lead performance analysis and optimization for CPU, memory, and virtualization subsystems in NIO’s embedded platforms.

Compensation

The US base salary range for this full-time position is $192,100.00 - $249,600.00.

Responsibilities

Identify and analyze performance bottlenecks across CPU, memory hierarchy, cache, interconnect, and interrupt subsystems.
Leverage hardware PMU counters to measure and interpret cycles, instructions, cache misses, branch mispredictions, TLB misses, and stall cycles.
Compute and analyze performance metrics such as IPC, CPI, MPKI, memory bandwidth utilization, and stall breakdowns.
Optimize system software, applications, and drivers for throughput, latency, and performance determinism.
Profile and reduce hypervisor overhead, including VM exits, interrupt injection, and stage-2 MMU translation costs.

Requirements

Bachelor’s in Computer Science
Master’s in Computer Science
Ph.D. in Computer Science
Bachelor’s in Electrical Engineering
Master’s in Electrical Engineering

Skills

CPU performance analysis Memory hierarchy optimization Cache optimization Interrupt architecture Linux perf eBPF ftrace C/C++Python shell scripting perf bcc bpftrace trace-cmd

Benefits

Anthem Blue Cross, HSA, and Kaiser HMO medical plans
Dental and vision plans
Company Paid HSA Contribution
Healthcare and Dependent Care FSA
401(k) with Brokerage Link option

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AI System Architect (NPU / GPU / Interconnect)

Qualcomm · Posted Nov 5, 2026

Shanghai, China
10+ years

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Architect next-generation AI and data center compute platforms with expertise in AI accelerators, GPUs, and high-performance interconnects.

Responsibilities

Engage with customers, partners, and internal stakeholders to understand AI workload requirements, deployment scenarios, performance targets, and system constraints.
Translate customer and market requirements into scalable system architecture, technology roadmaps, and platform features.
Drive architecture tradeoff analysis across performance, power, cost, scalability, and deployment requirements to influence product direction.
Analyze and optimize AI workloads including LLMs, Transformers, computer vision, multimodal AI, and recommendation systems.
Drive HW/SW co-design across architecture, compiler, runtime, driver, and framework layers.

Requirements

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field

Skills

AI accelerator architecture NPU architecture GPU architecture

graphics pipeline

compute architecture

high-performance interconnects

data center architecture

memory hierarchy optimization

HW/SW co-design

performance analysis

system architecture

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