- San Francisco, California, United States
- On-site
- 10+ years
Lead bench characterization, system-level validation, and technical customer enablement for advanced Smart Power Stages and controllers in AI data center architectures.
Responsibilities
- Lead hands‑on lab characterization, debugging, and performance optimization of Smart Power Stages, driver ICs, and multiphase controllers under real‑world AI workload dynamics.
- Evaluate and benchmark high‑frequency, high‑power density Si and GaN‑based power stages, optimizing for power density, transient response, efficiency, and thermal dynamics.
- Partner closely with IC Design, Package Engineering, Systems Engineering, and Product/Test teams to translate system requirements into silicon/module definitions and resolve complex silicon and packaging anomalies.
- Provide application‑level feedback on advanced power packaging technologies, including QFN, LGA, Fan‑Out Panel Level Packaging (FO‑PLP), and Chip‑Embedded / substrate‑embedded architectures.
- Deliver reference designs, evaluation boards (EVBs), application notes, and direct engineering support to top‑tier hyperscale and server OEM/ODM hardware teams.
Requirements
- B.S. in Electrical Engineering (M.S. or Ph.D. preferred with a focus on Power Electronics)