Performing static timing analysis jobs

Physical Design Engineer

Apple · Posted Nov 5, 2026

San Diego, California, United States
On-site
Full-time
$175K–$263K per year
2+ years

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Build full chip clock trees, perform specification generation, clock planning involving design and construction of recombinant networks, automate clock tree specification generation for clock construction and distribution across the dies to meet all the clock tree specifications, latency, and power, work with logic design team to understand partition architecture and drive physical aspects early in the design cycle, complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals, conduct timing, physical and electrical verification, and drive the signoff closure for the partitions, resolve design and flow issues related to physical design, identify potential solutions and drive execution.

Compensation

The base pay range for this role is between $175,000 - $263,300/yr and your base pay will depend on your skills, qualifications, experience, and location. This role might be eligible for discretionary bonuses or commission payments as well as relocation.

Responsibilities

Build full chip clock trees
Perform specification generation
Plan clock networks
Automate clock tree specification generation
Work with logic design team

Requirements

Master’s degree in Computer Engineering, Electrical Engineering, or related field

Skills

Building clock networks for high-performance CPU cores Analyzing interconnect delays, parasitics, and coupling Optimizing interconnect wire delays

Performing static timing analysis jobs

Compensation

Responsibilities

Requirements

Skills

Compensation

Responsibilities

Requirements

Skills

Benefits