- Chandler, Arizona, United States
- Full-time · Senior
- $110K–$176K per year
- 3+ years
Design and deploy ML, DL, and GenAI tools that translate silicon data into actionable optimized strategies for predictive yield and performance optimization.
Compensation
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Responsibilities
- Design, build, and deploy ML, DL, and GenAI models to predict and maximize wafer-level yield using large-scale SoC telemetry data.
- Organize, clean, and analyze large, multi-source sensor databases and provide input on future telemetry requirements.
- Interpret complex parametric data, on-chip sensor readouts, and circuit telemetry to isolate failure mechanisms and marginalities.
- Partner with foundry, product engineering, design-for-manufacturing (DFM), DFT engineering teams to drive yield and PPA strategies.
- Develop, qualify and productize experimental data workflows, and work with teams to release to scalable production.
Requirements
- MS in Electrical Engineering
- MS in Computer Science
- PhD in Electrical Engineering or Computer Science related field
- Nice to have: Stanford
- Nice to have: UC Berkeley