- San Jose, California, United States
- Hybrid
- Full-time · Mid
- $126K–$177K per year
- 2+ years
Signal and Power Integrity Engineer to develop next generation ASIC packaging, design rules, and validate high-speed interconnects.
Compensation
The starting salary range posted for this position is $125,700.00 to $176,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
- Develop, document, and implement design rules for ultra-high-speed signaling
- Analyze substrate signal integrity and power integrity
- Design, document, and develop ASIC packages
- Collaborate with system partners, vendors, and design leads
Requirements
- Bachelor's degree
- Master's degree
- Nice to have: High-Bandwidth Memory
- Nice to have: HBM
- Nice to have: Die-to-die interfaces