- San Jose, California, United States
- Full-time · Senior
- $173K–$295K per year
- 5+ years
Develop next-generation NAND error correction and decoding technologies, including LDPC/BCH, hard/soft decoding, and channel/LLR estimation, and evaluate algorithms and architectures optimized for reliability, latency, throughput, power, and area.
Compensation
$173,000.00 - $295,000.00 a year
Responsibilities
- Develop ECC strategies and integration solutions, evaluating the impact of BCH, LDPC, and other solutions on area, latency, power consumption, and error correction capabilities.
- Analyze NAND channel characteristics. Develop and evaluate advanced error-handling techniques.
- Evaluate ECC impact on system-level metrics.
- Explore next-generation ECC/data-processing architectures for future NAND and AI/storage products.
Requirements
- MS or PhD in Electrical Engineering, Computer Engineering, or related field
- Nice to have: NAND Flash
- Nice to have: SSD/controller architecture
- Nice to have: AI