Master Thesis: Hardware-in-the-Loop Methodology for PMIC Verification
Infineon · Posted Nov 11, 2026
- Padua
- Internship · Intern
Define and develop a scalable Hardware-in-the-Loop (HIL) methodology for automated PMIC verification and contribute to creating a reusable verification framework.
Responsibilities
- Define and develop a scalable Hardware-in-the-Loop (HIL) methodology for automated PMIC verification
- Contribute to creating a reusable verification framework that supports efficient and reliable validation of PMIC functionality under different operating conditions
- Develop a behavioral model of the PMIC describing the expected response to analog and digital stimuli
- Define a scalable test methodology to automatically stimulate the Device Under Test with analog and digital signals, including fault injection scenarios
- Implement an automated verification framework to compare the actual device response against the expected behavioral model
Requirements
- Master’s in electrical/electronic engineering or related technical field
- Nice to have: PCB design
- Nice to have: PCB layout