- Penang, Malaysia
- Senior
- 10+ years
Design and validate timing models for FPGA and ASIC IP, ensuring alignment with tool specifications and product requirements.
Responsibilities
- Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
- Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
- Perform quality checks on timing models to confirm all timing arcs meet software requirements.
- Address issues such as missing timing arcs and missing clock information.
- Generate timing reference models based on IP requirements.