- Austin, Texas, United States
- On-site
- Full-time
- $203K–$215K per year
- 7+ years
Compensation
Salary Range $202,779 - $215,300 / year.
Responsibilities
- Design and validate high-bandwidth memory and DDR memory physical layer interfaces for machine learning accelerator chips and system-on-chip architectures
- Integrate third-party intellectual property blocks into complex system-on-chip designs and perform advanced 2.5D packaging design for memory subsystems
- Perform post-silicon validation and characterization of memory subsystems including bring-up, debug, and performance optimization
- Define and implement boot-up initialization sequences, reset flows, and training algorithms for memory controllers and physical layer circuits
- Collaborate with physical design teams to define timing constraints and review clock distribution networks for memory interfaces
Requirements
- Master’s degree in Electrical Engineering or Computer Engineering
- Bachelor’s degree in Electrical Engineering or Computer Engineering