- Allen, Texas, United States
- Senior
- 10+ years
Lead the design, simulation, verification, and delivery of power management and clocking analog IP blocks for Treo-based SoC platforms.
Responsibilities
- Design, simulate, and verify power management IP including LDOs, DC/DC converters, and charge pumps.
- Design and implement clocking circuits such as PLLs, DLLs, oscillators, and clock distribution networks.
- Support IP architecture definition by contributing analysis, trade‑off studies, and design proposals.
- Execute schematic design, layout guidance, post‑layout extraction, and corner/Monte Carlo analysis to meet specifications.
- Deliver validated analog blocks into mixed‑signal and digital‑on‑top subsystems for SoC integration.
Requirements
- Nice to have: Verilog‑A/AMS/SV RNM modeling
- Nice to have: automotive reliability
- Nice to have: industrial reliability
- Nice to have: functional‑safety requirements
- Nice to have: AI/ML‑assisted design