- Hyderabad, Telangana, India
- Senior
- 5+ years
Senior Engineer responsible for timing constraints (SDC) development and maintenance for complex SoC designs.
Responsibilities
- Own and manage timing constraints (SDC) development and maintenance for complex SoC designs.
- Define and manage clocks, clock relationships, and timing exceptions using XML-based or equivalent constraint methodologies.
- Develop, review, and validate timing constraints with strong focus on quality and accuracy.
- Independently manage and enhance constraint build flows and automation methodologies.
- Perform debug and analysis related to GCA, TCM, minimum pulse width, and minimum period violations.
Requirements
- Nice to have: SerDes-based protocols
- Nice to have: high-speed interfaces
- Nice to have: protocol specifications
- Nice to have: advanced SoC design flows
- Nice to have: industry-standard STA tools