Execute and track electrical validation test plan strategies of the Analog Front End (AFE) and end-to-end interconnections across Intel Xeon D platforms.
Perform test setups and configurations across interfaces such as Networking (Eth, CPRI) and Mem (DDR5, LPDDR5x).
Validate conformance to networking and JEDEC industry standards and Intel specifications.
Apply Intel developed validation disciplines, including Signal Integrity (SI) Validation, System Marginality Validation and/or Interoperability methodologies and processes.
Develop debug documentation with lab experiences during execution and system issues resolution.
Requirements
Bachelor's degree in electrical engineering, Computer Engineering, or a related field.
Nice to have: Master's degree in electrical engineering, Computer Engineering, or a related field.
Nice to have: proficiency in Memory technologies (RDIMM, UDIMM, SODIMM, MRDIMM)
Nice to have: networking protocols (Ethernet, CPRI technologies)
Nice to have: familiarity with debugging tools and validation methodologies
Lead technical program management for new cloud services and hardware platforms, driving delivery, quality, and scalability.
Locations (3)
Redmond, Washington, United States
San Francisco, California, United States
New York City, New York, United States
Compensation
The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Manage introduction of new cloud services, hardware platforms and tools/processes
Work with partner engineering teams to meet scale and cycle time specifications
Analyze data to prototype and implement technical and process improvements
