- Hsinchu, Taiwan, Taiwan
- Full-time · Senior
- 20+ years
Lead the development of design debug, analysis, and visualization tools for simulation and emulation solutions.
Responsibilities
- Architect, design, and enhance frontend EDA tools for RTL/gate‑level debug, waveform analysis, and design visualization.
- Drive performance, capacity, and usability improvements for large‑scale SoC designs.
- Establish and maintain baseline performance metrics for interactive editing, debugging, and analysis flows.
- Lead investigation and resolution of complex customer design issues involving RTL, netlists, timing, and simulation data.
- Act as a technical owner for key frontend initiatives, from concept through deployment.
Requirements
- MS in Computer Science, Electrical Engineering, or equivalent practical experience.
- Nice to have: FPGA‑based prototyping
- Nice to have: emulation systems
- Nice to have: cross‑site engineering teams
- Nice to have: patents or publications related to EDA