- Goleta, California, United States +1 more
- On-site
- Full-time · Senior
- $174K–$252K per year
- 2+ years
Locations (2)
- Goleta, California, United States
- Los Angeles, California, United States
Compensation
US: $174000 - $252000 (USD) + 15% bonus target + equity + benefits
Responsibilities
- Evaluate logical performance of proposed processor architectures (including novel QEC codes, modular and multiplexed control schemes, and alternative superconducting qubit or gate designs) prior to fabrication
- Develop and adapt models of correlated physical error mechanisms, such as leakage and two-level system (TLS) defects, to build realistic logical error budgets beyond simplified noise models
- Architect, build, and maintain modular end-to-end Python simulation pipelines that bridge electromagnetic and device-level physics models with processor noise models and circuit-level QEC simulations
- Partner closely with processor design, device modeling, and QEC protocol teams to drive processor design trade-offs and actionable hardware roadmap recommendations