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Verification Engineer 4
Sunrise Systems Inc · Austin, US

+10K new in the last hour

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Verification Engineer 4

Sunrise Systems Inc · Posted Sep 3, 2026

Austin, Texas, United States

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Requirements

Nice to have: Nice to have

Skills

VC Formal (Synopsys)Jasper Gold (Cadence)System Verilog Assertions (SVA)formal property specification formal verification applications FPV connectivity checking register verification equivalence checking coverage analysis scripting languages (TCL, Python, Perl)flow automation

design verification

formal verification

UVM-based verification methodologies

,TX,Austin 12 Months Description: PREFERRED EXPERIENCE: Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) Strong proficiency in System Verilog Assertions (SVA) and formal property specification Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis Familiarity with scripting languages (TCL, Python, Perl) for flow automation Extensive experience in design verification with a strong focus on formal verification Expertise in System Verilog and UVM-based verification methodologies - Nice to have

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