- Pune, Maharashtra, India
- Senior
- 8+ years
Lead Zephyr RTOS architecture and platform enablement for MIPS RISC-V based MCU and embedded compute products.
Responsibilities
- Own the Zephyr enablement architecture and technical roadmap across MIPS RISC-V processors, SoCs, FPGA platforms, and virtual development platforms.
- Lead porting and platform bring-up covering boot flow, exception and interrupt handling, timers, SMP where applicable, memory architecture, devicetree, Kconfig, and build integration.
- Define scalable BSP, SoC, board, and driver architecture aligned with Zephyr conventions and upstream-quality expectations.
- Design and review device drivers, middleware integration, samples, tests, and production-quality SDK deliverables.
- Lead complex debugging across kernel, toolchain, architecture, hardware, and driver boundaries using emulation, FPGA, and silicon.
Requirements
- Nice to have: RISC-V architecture
- Nice to have: privilege modes
- Nice to have: interrupts
- Nice to have: timers
- Nice to have: SMP