- Bengaluru, Karnataka, India
- On-site
- Senior
- 8+ years
Shape the future of AI/ML hardware acceleration by designing and verifying DFT strategies for TPU architecture.
Responsibilities
- Develop DFT strategy and architecture
- Develop and drive die level DFT validation strategy
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block
- Document DFT architecture, test sequences, and boot-up sequences
- Generate and deliver production and debug patterns to Post Silicon engineering team
Requirements
- Bachelor's degree in Electrical Engineering
- Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
- Nice to have: IP integration
- Nice to have: fault modeling
- Nice to have: SoC cycles