- Santa Clara, California, United States
- On-site
- Full-time · Entry
- $106K–$149K per year
- 0+ years
Entry Level Design Verification Engineer to build a configurable interconnect and chassis generator for SoCs and chiplets within the Unified Intel Chassis (UIC) team.
Compensation
Annual Salary Range for jobs which could be performed in the US: $105,650.00-149,150.00 USD
Responsibilities
- Develop simulation tests, formal properties, reference models, and checkers for interconnect and chassis IP
- Debug simulation failures and formal counterexamples
- Translate specifications into verification plans and checks
- Participate in architecture and design discussions
- Build scripts and reusable tools for configuration generation, regression execution, and results analysis across generated designs
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- Nice to have: RTL simulation
- Nice to have: formal verification
- Nice to have: SystemVerilog assertions
- Nice to have: UVM