- Hsinchu City, Taiwan
- On-site
- Senior
- 2–10 years
Lead ASIC design and delivery for Ethernet switch subsystems, driving architecture-aligned implementation, optimization, and integration.
Responsibilities
- Implement RTL design, synthesis, and timing closure for networking datapath/control logic
- Participate in SoC integration with focus on Ethernet switch subsystems
- Lead design and delivery of key subsystems in Ethernet switch ASICs
- Own micro-architecture and RTL design of networking blocks
- Drive subsystem integration, performance tuning, and power optimization
Requirements
- Bachelor's degree in Science, Engineering, or related field
- Master's degree in Science, Engineering, or related field
- PhD in Science, Engineering, or related field