- Tokyo, Tokyo, Japan
- Senior
- 2+ years
Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
Responsibilities
- Interpret product specifications and test requirements; define circuit functionality, interfaces, operating limits, controllability, observability, and validation criteria.
- Create, review, and optimize schematics, device sizing, bias structures, sensing and monitoring paths, multiplexers relevant to test circuits.
- Analyze circuit testability and robustness to ensure compliance with quality, coverage, manufacturability, power, area, and reliability.
- Validate custom test circuits using XA simulation, Verilog simulation, and mixed-signal verification environments.
- Collaborate closely with layout teams on matching, parasitic sensitivity, shielding, routing, guard rings, device placement, and layout-dependent effects.
Requirements
- Electrical Engineering
- Electronics Engineering
- Computer Engineering
- Nice to have: NAND flash memory architecture
- Nice to have: Test modes