- San Jose, California, United States +7 more
- Senior
- $164K–$231K per year
- 9+ years
1–3 jobs· newest first
$164K–$231KSenior

$175K–$263KOn-site · Full-time
Senior
+10K new in the last hour
Lead technical design and architecture of mixed-signal SoC products, overseeing development, integration, verification, and post-silicon bring-up.
MaxLinear's good faith estimate starting base salary range is: $164,000 to $231,000 Annually
Build full chip clock trees, perform specification generation, clock planning involving design and construction of recombinant networks, automate clock tree specification generation for clock construction and distribution across the dies to meet all the clock tree specifications, latency, and power, work with logic design team to understand partition architecture and drive physical aspects early in the design cycle, complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals, conduct timing, physical and electrical verification, and drive the signoff closure for the partitions, resolve design and flow issues related to physical design, identify potential solutions and drive execution.
The base pay range for this role is between $175,000 - $263,300/yr and your base pay will depend on your skills, qualifications, experience, and location. This role might be eligible for discretionary bonuses or commission payments as well as relocation.
Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.