- Taipei, Taiwan, Taiwan +1 more
- On-site
- Full-time · Senior
- 3+ years
Drive the next generation of AI-assisted silicon development, combining traditional RTL design and verification expertise with AI/ML technologies to improve engineering productivity, quality, and development efficiency across the silicon lifecycle.
Locations (2)
- Taipei, Taiwan, Taiwan
- Hsinchu, Taiwan, Taiwan
Responsibilities
- Develop and maintain high-quality RTL in Verilog/SystemVerilog for ASIC/SoC products
- Participate in architecture definition, microarchitecture development, implementation, and integration
- Develop UVM-based verification environments, test plans, testcases, assertions, and coverage models
- Debug functional, performance, and integration issues across IP, subsystem, and SoC levels
- Develop AI agents and copilots to accelerate RTL design, verification, debug, code review, and productivity workflows
Requirements
- BS or above degree in Electrical Engineering, Computer Engineering, Computer Science, or related field