Lead FPGA-based modeling for mixed-signal IPs and system platforms, bridging hardware and software, and driving verification and architecture exploration.
Locations (2)
Munich, Bavaria, Germany
Bengaluru, Karnataka, India
Responsibilities
Drive FPGA-based modeling for mixed-signal IPs and comprehensive system platforms
Bridge the gap between hardware and software by developing robust FPGA models that enable early firmware validation system-level verification and architecture exploration
Architect real-number models on FPGA
Automate workflows
Work hands-on with hardware prototypes to ensure our mixed-signal platforms meet rigorous performance and functionality standards
Requirements
Bachelor’s in Electronics Electrical Engineering Computer Engineering or a related field
Master’s in Electronics Electrical Engineering Computer Engineering or a related field
Stage - Conception et prototypage d'IP numériques/SoC - F/H
Stage de 6 mois contribuant au développement de la prochaine génération d’IP semi-conducteurs et de plateformes SoC, de l’architecture RTL à l’implémentation sur silicium.
Responsibilities
Contribuer à la conception et au développement d’IP numériques avancées et de sous-systèmes SoC.
Participer aux études d’architecture et à la définition de microarchitectures pour des interfaces numériques haut débit, notamment les solutions de communication Die-to-Die (D2D).
Développer, intégrer et vérifier des conceptions RTL en utilisant les méthodologies de vérification standard de l’industrie.
Participer au prototypage sur FPGA, à la mise en route (bring-up) et à la validation d’IP numériques et de sous-systèmes.
Contribuer à l’analyse des performances, au débogage et à l’optimisation des conceptions sur plateformes FPGA.
Lead pre‑silicon verification for security IP blocks and SoC subsystems, designing test environments, driving coverage, and coordinating with customer and partner teams.
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Own pre‑silicon verification strategy and execution for security IP blocks and subsystems
Architect and extend SystemVerilog and UVM environments
Drive coverage signoff across functional, code, and power‑aware coverage
Act as verification lead and technical point of contact for customer and partner teams
Develop C and C++ test content, low‑level drivers, and custom firmware
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Staff Engineer focused on verifying advanced Ethernet and PCIe SERDES IP using AMS co-simulation, UVM-based testbenches and automation.
Responsibilities
Define and execute verification test plans for Ethernet and PCIe SERDES IP, tracking coverage metrics and ensuring completeness across functional, analog, and mixed-signal scenarios
Build and maintain UVM-based SystemVerilog testbenches integrated with AMS co-simulation flows, combining RTL, behavioral models, and transistor-level netlists into unified verification platforms
Verify SERDES subsystems including TX/RX datapaths, equalization algorithms, CDR loops, PLL locking behavior, and analog-digital interface interactions across process corners and operating conditions
Debug simulation failures that span analog, digital, and mixed-signal domains using tools like HSPICE, XA, CustomSim, and VCS
Perform design reliability checks including electromigration, IR drop analysis, and device-level stress evaluations to ensure robustness in production silicon
Lead the development and execution of robust, reusable UVM verification environments for our products, ensuring functional‑coverage and first‑silicon success.
Locations (2)
Rennes, Brittany, France
Paris, Île-de-France, France
Compensation
An attractive compensation package, including a competitive salary, variable compensation, and meal vouchers
Responsibilities
Define and implement robust, scalable UVM test‑bench architectures for complex digital IPs
As a Lead (Staff) Designer, Digital, you hold a senior technical position working on our most complex digital challenges, developing innovative solutions and serving as a key technical resource and leader for the organization.
Responsibilities
Architect and design digital blocks and complex subsystems.
Write detailed block and subsystem-level specifications for design and implementation.
Use Verilog and SystemVerilog to design digital blocks, subsystems, and top level designs.
Develop block level testbenches, verify block functionality, and collaborate with verification teams to achieve full chip verification and coverage closure.
Perform block and top level linting, CDC analysis, and power analysis. Assist with synthesis, constraints, pnr and timing closure.
Requirements
MSEE
PhD in Electrical Engineering
Nice to have: high-speed SerDes transceiver architectures
The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead the architecture and design of complex CPU subsystems for next‑generation high‑performance networking switch ASICs
Use expertise in all stages of ASIC development from specification and RTL design through post‑silicon bring‑up
Collaborate closely with SDK, board‑support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms
Requirements
Bachelor's degree
Master's degree
PhD
Nice to have: Leading CPU/SoC subsystem architecture
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