- San Francisco
Design and develop next-generation AI accelerator silicon RTL.
Responsibilities
- Design and implement high-performance RTL for next-generation AI accelerator silicon
- Collaborate with architecture and software teams to translate system-level requirements into efficient hardware microarchitectures
- Drive hardware/software co-design efforts to optimize performance, power, area, and scalability for AI workloads
- Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems
- Evaluate architectural and microarchitectural tradeoffs across bandwidth, latency, throughput, and resource utilization