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Staff Engineer, Digital ASIC Design — Storage Controllers
SK hynix memory solutions America Inc. · Posted Nov 10, 2026
- San Jose
- Staff
Lead and own digital ASIC blocks from requirements through RTL implementation, verification, and silicon delivery for next-generation SSD controllers and storage solutions.
Compensation
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
Responsibilities
- Own digital ASIC blocks from requirements and microarchitecture definition through RTL implementation, verification support, and silicon delivery.
- Develop clear microarchitecture specifications documenting interfaces, data flows, design tradeoffs, and implementation details.
- Write synthesizable Verilog or SystemVerilog RTL that meets functional, performance, power, and area requirements.
- Run and resolve findings from RTL lint, clock domain crossing (CDC), and synthesis tools to improve design quality.
- Collaborate with design verification engineers to develop verification plans, debug simulations using tools such as Synopsys VCS, and resolve functional issues.
Requirements
- Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
- Nice to have: PCIe
- Nice to have: NVMe
- Nice to have: SSD controller architectures
- Nice to have: NAND interfaces