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1–2 jobs· newest first

ASIC Design Verification Engineer, Machine LearningNew
Google · Sunnyvale, US
$138K–$197KOn-site · Full-time · Mid
ASIC Design Verification Engineer, Google TPU
Google · Sunnyvale, US
$138K–$197KOn-site · Full-time · Mid

+10K new in the last hour

ASIC Design Verification Engineer, Machine Learning

Google · Posted Nov 10, 2026

Sunnyvale, California, United States
On-site
Full-time · Mid
$138K–$197K per year

4–5 years

Apply with RefersoAI Apply on careers page

ASIC Design Verification Engineer focused on AI/ML hardware acceleration and TPU (Tensor Processing Unit) technology for data centers.

Compensation

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Nice to have: computer architecture
Nice to have: silicon-based ICs and chips

Skills

SystemVerilog Verilog UVM SystemVerilog Assertions (SVA)ASIC standard interfaces memory system architecture SVA

Benefits

benefits

See full job description

ASIC Design Verification Engineer, Google TPU

Google · Posted Nov 5, 2026

Sunnyvale, California, United States
On-site
Full-time · Mid
$138K–$197K per year
4+ years

Apply with RefersoAI Apply on careers page

ASIC Design Verification Engineer focused on TPU architecture and integration within AI/ML systems

Compensation

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Identify and write all types of coverage measures for stimulus and corner cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Create a constrained-random verification environment using SystemVerilog and UVM.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Nice to have: 6 years of experience with silicon design verification

Skills

design verification SystemVerilog Verilog

silicon design verification

industry-standard simulators

revision control systems

regression systems

ASIC standard interfaces

Benefits

equity
benefits

See full job description