- Boxborough, Massachusetts, United States
- Full-time · Senior
This role offers a rare opportunity for a senior technical leader to shape the future of memory interface technology at scale. As a key architect within the AMD Circuit Technology Design Group, you will influence the definition, architecture, and delivery of next-generation Memory PHY solutions in advanced CMOS technologies.
Responsibilities
- Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.
- Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.
- Drive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity.
- Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide.
- Influence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions.
Requirements
- Advanced degree in Electrical Engineering or related field preferred, or equivalent professional experience
- Nice to have: Sustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes
- Nice to have: Owning or shaping architecture across multiple successful tape-outs