This role focuses on mixed signal high-speed PHY post-silicon validation and debug, spanning IP enabling, customer sighting resolution, and cross-functional collaboration with SOC teams.
Locations (2)
Folsom, California, United States
Santa Clara, California, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
Responsibilities
Generate test plans and test content for mixed signal high-speed PHY post-silicon validation, including characterization of Clocking, Transmitter, and Receiver blocks
Perform IO protocol debug across one or more of the following: PCIe, UCIe, DDR, or Ethernet, from both PHY recipe and firmware perspectives
Conduct SOC board design reviews, provide recommendations, and support post-silicon debug activities
Represent the IP team during SOC Power-Ons for test chips and products, providing hands-on IP enabling support through proper recipes and firmware versions for PCIe, UCIe, and USB PHYs
Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.
Compensation
Base Pay Range
218,889.00
Responsibilities
Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
Analyzing hardware capabilities and contributing to customer solution strategies.
Architecting Soft IPs with detailed technical specifications and coordinating development efforts.
Requirements
Bachelor’s degree in Electronics Engineering, Applied Physics or related field
Execute complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews and close tracking of technical as well as management aspect
Provide guidance to team on developing UVM-based SV test-benches, defining block, sub-system and SOC top level test plans, PCIe, NVMe, NAND, DDR and CPU sub-systems and verification methodologies, flows and quality metrics.
Execute complete verification project as a senior engineer with hands‑on experience, mentoring, client communication, in‑depth technical reviews and close tracking of technical and management aspects
Provide guidance to team on developing UVM‑based SV test‑benches, defining block, sub‑system and SOC top‑level test plans, PCIe, NVMe, NAND, DDR and CPU sub‑systems and verification methodologies, flows and quality metrics
Work independently with minimal guidance, solve complex problems, act as a resource for less experienced colleagues, contribute to process improvements, and provide informal guidance to junior staff
Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning.
Experience with Verilog, VHDL design Knowledge
Experience with C/C++, DPI and System Verilog add on.
Experience writing scripts using any languages (Perl, Python, Makefile )
Experience with waveform debug tools, Verdi/SimVision.