- San Jose, California, United States
- $160K–$200K per year
- 5+ years
Lead the development of next-generation connectivity ASICs for cloud and AI infrastructure, focusing on Physical Design CAD methodology and automation.
Compensation
The base salary range for this role is $160,000–$200,000 USD.
Responsibilities
- Develop and maintain Physical Design CAD flows and methodologies for advanced process nodes.
- Build automation frameworks using Python and Tcl to support synthesis through signoff.
- Perform hands‑on Physical Design and PNR, including floorplanning, placement, CTS, routing, and timing closure.
- Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
- Support block‑level implementation from synthesis through GDSII signoff.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's degree preferred.
- Nice to have: 3nm or more advanced process technologies
- Nice to have: Automated CAD flows from synthesis through signoff
- Nice to have: Cadence Innovus
- Nice to have: Tempus