Design and develop digital portions of battery gauge mixed-signal SOCs, from micro-architecture to RTL and production-ready hardware.
Responsibilities
Collaborate with system and analog design to define digital micro-architecture specifications and implement the RTL that realizes them.
Drive the full digital flow from RTL to physical layout (RTL-to-GDSII), applying and advancing industry best practices, and guide fellow team members through it.
Partner with Design Verification, Validation, Product Engineering, and Test Engineering to ensure a smooth, first-pass transfer to production.
Interface with internal and external stakeholders to understand design requirements, solve problems, and lead technical discussions.
Explore opportunities to optimize and improve digital designs and help evolve architectures over time.
Responsible for RTL design and SoC integration of digital IP blocks for advanced SoC products in high-performance computing, networking, security, embedded systems, and data-centric applications.
Responsibilities
RTL design and development of digital IP blocks
SoC integration and subsystem ownership
Architectural exploration and protocol evaluation
Collaboration with verification, physical design, validation, and software teams
Optimize designs for performance, power, and area targets
Requirements
B.Sc. or M.Sc. in Electrical or Computer Engineering
Lead the development of next-generation connectivity ASICs for cloud and AI infrastructure, focusing on Physical Design CAD methodology and automation.
Compensation
The base salary range for this role is $160,000–$200,000 USD.
Responsibilities
Develop and maintain Physical Design CAD flows and methodologies for advanced process nodes.
Build automation frameworks using Python and Tcl to support synthesis through signoff.
Perform hands‑on Physical Design and PNR, including floorplanning, placement, CTS, routing, and timing closure.
Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
Support block‑level implementation from synthesis through GDSII signoff.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's degree preferred.
Nice to have: 3nm or more advanced process technologies
Nice to have: Automated CAD flows from synthesis through signoff
Own and maintain the internal design backend API and qubit design framework, develop new parametric components, extend export pipeline, build automation layer, support internal users.
Compensation
Our success is your success: own it with our BSPCE plan
Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.
Responsibilities
Own and maintain the internal design backend API and qubit design framework: code quality, testing, CI, releases, documentation
Develop new parametric components and layout primitives with the chip designers who use them
Extend and harden the export pipeline to electromagnetic and circuit simulation tools
Build the automation layer for large-scale, hierarchical chip layouts in close partnership with our physical-design and scale-up engineers
Support internal users: onboarding, debugging, API design, and turning recurring pain points into features
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