- San Diego, California, United States
- On-site
- Full-time · Mid
- $122K–$183K per year
- 2+ years
The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency.
Compensation
$121,800.00 - $182,600.00
Responsibilities
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products.
- Create architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
- Collaborate across teams to develop and execute an implementation strategy that meets system requirements and customer needs.
- Evaluate all aspects of process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
- Utilize tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable architecture and design of an individual block/SoC or IC Package.
Requirements
- Bachelor's degree in Engineering, Science, or a closely related field
- Master's degree in Science, Engineering, or related field
- PhD in Science, Engineering, or related field