- Paris, Île-de-France, France +1 more
- On-site
- Full-time · Senior
- 5+ years
Lead verification of complex ASIC and SoC IP blocks for AR hardware.
Locations (2)
- Paris, Île-de-France, France
- Eindhoven, North Brabant, Netherlands
Compensation
Competitive compensation and comprehensive benefits, including parental leave, medical coverage, mental health support, and phone and fitness allowances.
Responsibilities
- Own verification of complex IP blocks and subsystems from specification through sign-off
- Build and maintain UVM/SystemVerilog verification environments
- Develop constrained-random tests, coverage plans, assertions, and verification strategies
- Drive functional and code coverage to closure
- Partner closely with design, architecture, firmware, and other engineering teams to refine requirements and debug issues